Researchers from the University of California in the month of November 2018, Santa Barbara, the head presented a paper on CMOS-compatible graphene interconnects.
Following that work, a team of the University of California Santa Barbara (UCSB) engineering researchers recently came out with a method to utilize nanometer-scale doped multilayer graphene (DMG) interconnects well suited to the mass-production of integrated circuits.
Over 20 years interconnects have been manufactured using copper as the base material, yet, the limitations of this metal when shrinking it to the nanoscale resistivity increase, which poses a fundamental threat to the $500 billion semiconductor industry, according to the researchers at UCSB.
Graphene holds the potential to resolve this issue as a global desire for smarter, faster, lighter and affordable technology and it continues to expand states AZONANO.
According to the words of Kaustav Banerjee, a professor in the Department of Electrical and Computer Engineering, When you reduce the dimensions of copper wires, their resistivity shoots up. Resistivity is a material property that is not supposed to change but at the nanoscale. The UCSB team now believes it has found a promising method to use graphene for interconnects.
Well, it is not a case of simply replacing copper with graphene in the manufacturing process as research is still being carried out. Therefore, transposing the material from the university or other facility testing environments to high-volume production and wide-spread usage is yet another obstacle that must be overcome
Now, after a decade of attempt, Professor Banerjee’s lab has developed an innovative pressure-assisted solid-phase diffusion method that allows the direct synthesis of high-quality multi-layer graphene compatible with typical standard industry processes for the mass production of integrated circuits.
A method that needs the application of pressure and temperature to two materials in close contact so as to cause them to diffuse into one another. So, overcoming the bottleneck of risking damage or diffusing any impurities to other elements present on the chips to keep the characteristics of the transistors intact.
The process began with the UCSB team depositing solid-phase carbon in the form of graphite onto a deposited layer of nickel-metal of optimized thickness. Then, exposing the graphite powder to heat (about 300 degrees Celsius) and pressure caused disintegration in the graphite.
The high diffusivity of carbon in nickel enables it to move quickly through the metal film-forming multiple graphene layers as the carbon atoms then recombine on the other surface of the nickel closer to the dielectric substrate.
The challenge, according to the researchers, is getting the tech-giants such as Intel, who develop a vast amount of chips each year with great profits, to accept replacing copper with graphene into its manufacturing process.
UCSB’s Banerjee has kept in negotiations with industry partners who have demonstrated an interest in licensing the compatible graphene synthesis technology, which could pave the way for what would be the first 2D material to enter the mainstream semiconductor industry.